Circuits can be designed accommodate different clocking schemes. These clocking schemes are usually a reflection of the characteristics of the underlying storage element - edge sensitive or transparent (level sensitive) flip-flops and latches.

Edge Sensitive Flip-Flops - While larger (more transistors) than their level-sensitive counter parts, edge-sensitive flip-flops have come to dominate many areas of digital circuit design. Their early use in TTL (7474), their adoption in PLD and CPLDs, and the ubiquitous use in FPGAs have made them very popular.

An edge-sensitive flip-flop is sensitive to changes in around the clock edge. At other times changes on the D input (we will discuss only D type flip-flops - refer to a logic text if your memory is vague on their operation) are ignored - in other words not reflected on the Q output.

That is pretty basic information - edge-sensitive flip-flops allows the construction of complex digital circuits that use only one clock and have a very simple clocking scheme - the relationship between the clock, data, and control signals.

Here is a simple circuit consisting of a register and an adder. The circuit simple increments the content of the register each time it is clocked.

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Assuming LOAD is true, when clock goes high (on the rising-edge) X appears at the output of the register, propagates around the circuit, and arrives at the input of the register as X+1.

As long as the path through the circuit to generate X+1 takes less time than the period of the clock, on the next rising edge of the clock X+1 will be clocked into the register, and the process can repeat.

The critical path (the longest path) must be shorter than the clock period. So for example if our adder had a delay of 25ns our clock would have to have a period longer than 25ns or could run no faster than 40 Mhz. This is a great simplication - we have not considered the progagation delay of the wires or the register!

Because new values of Q appear on the output of a flip-flop a few nanoseconds after the rising clock edge, on each clock edge, the data currently at the input of the register under control of the control logic setup on the previous edge of the clock, is latched into the registers.

So on each clock edge the control logic setups the control signals to control data flowing through the circuit, the data propagates through the circuit and is latched on the next clock edge. Data at the output of registers appears to be one clock cycle behind the control signals that cause it.

Here is the timing for our simple increment circuit with a control unit clocked on the same edge as the datapath register.

Notice that controls signals (RESET and LOAD) update the register on the clock edge after the one that generated them.

Two-phase Clocks

Some day....